1. Technical Field of the Invention
The present invention relates in general to data processing flows, and in particular to the adaptation of a bit rate in a data processing flow.
2. Description of Related Art
A bit rate adaptation takes place when a function implemented in the data processing flow modifies the data rate, i.e., when the average amount of data varies between the input and the output of the function. The presence of functions for bit rate adaptation in a processing flow makes its time behavior unpredictable. When the processing flow involves a plurality of bite rate adaptation functions in series, it is difficult to implement at the hardware level. Indeed, a large number of possible configurations must be tested in order to provide an interruption-free processing flow.
Software management of the processing flows is generally used for reduced rates, for example less than one Mbit/s. FIGS. 1 and 2 diagrammatically show such an operation. A general use processor 1, a storage 2 and an interface 4 communicate via the bus 3. The processor 1 is used to sequentially process all of the functions required by the processing flow. Each function of the processor 1 is assigned a dedicated storage location 2. The interface 4 transmits, to the processor 1, a data block to be processed by a function. The function then processes the data block in the processor 1 (for example, by modification, addition or deletion of data). When the function has completed the processing of the block, the modified data block is placed in the dedicated storage location 2. Another function of the processing flow is then launched. A data block is transferred from a dedicated storage location 2 to the processor 1, processed by the function in the processor 1, then transferred to the dedicated storage location. This software solution is relatively easy to debug and develop.
However, the software solution increases the cost of hardware components: this solution requires a processor that is effective enough to implement all of the functions of the flow: such a processor is generally optimized for the specific applications intended by the processing flow. In addition, the amount of memory must be adequate to store a complete data block for each of these functions.
According to an improvement, the storage 2 consists of a small internal cache and a slower, less expensive, larger external storage. Contiguous program data blocks are stored in the internal cache. However, the response time and the power dissipation are generally increased due to the additional transfers caused between the cache and the external storage.
For apparatuses requiring high processing speeds with lower power dissipation (for example, portable apparatuses such as mobile telephones according to the 3GPP standard), a mixed software/hardware solution is preferred. FIGS. 3 and 4 show its operation. The processing of specific functions is thus allocated to an acceleration circuit 5. The acceleration circuit 5 communicates with the general use processor 1 and the storage 2 by means of the bus 3. The processor 1 implements a software processing of a certain number of functions, while other critical functions are processed as desired in the acceleration circuit 5. For example, for a video restitution application, a function associated with the image decompression will be considered to be a critical function.
In a first step, a first block is transferred from the interface 4 to the processor 1. In a second step, a function processes this block in the processor 1. In a third step, this block is transferred to the storage 2. In a fourth step, a block associated with a critical function is transferred from the storage 2 to the acceleration circuit 5. In a fifth step, the critical function processes the block in the acceleration circuit 5. In a sixth step, this block is transferred from the acceleration circuit 5 to the storage 2. Depending on the case, a certain number of transfers between the storage and the acceleration circuit 5 or the processor 1 are performed for the processing of critical or non-critical functions.
When all of the functions are considered to be critical, a hardware solution is adopted. The operation of this solution is shown in FIGS. 5 and 6. When the processing flow is in series (i.e., when the operation sequence can be determined in advance, even if some functions are short-circuited so as to comply with certain operation requirements), the processing operations are performed only by one or more dedicated acceleration circuits 5 forming a processing flow chain by means of intermediate buffer storages 2.
The performance of this solution is superior to that mentioned above. Moreover, its power consumption is lower because only the functions required by the processing flow are integrated into the chain.
However, the development of such a chain is costly. Its architecture is more difficult to develop and may make it necessary to redefine the design of the integrated circuits when they do not have enough available surface. Moreover, as this solution is only hardware transcription of a software solution, significant amounts of memory and data transfers between the acceleration circuits and the storages are still necessary. A functional analysis shows that such an architecture has an amount of intermediate buffer storage that is not essential for the implementation of the functions, but that facilitates the hardware design and development. This memory amount occupies a substantial circuit surface and generates an unnecessary current consumption.
There is accordingly a need to solve one or more of these disadvantages.